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CXP88452/88460 cmos 8-bit single chip microcomputer description the CXP88452/88460 is a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time-base timer, high precision timing pattern generation circuit, pwm output, viss/vass circuit, 32khz timer/counter, remote control receiving circuit, vsync separator and the measurement circuit which measure signals of capstan fg and drum fg/pg and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also, the CXP88452/88460 provides sleep/stop functions which enable to lower power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation 122s at 32khz operation incorporated rom capacity 52k bytes (CXP88452) 60k bytes (cxp88460) incorporated ram capacity 2048 bytes peripheral functions ?a/d converter 8 bits, 12 channels, successive approximation system (conversion time of 20s/16mhz) ?serial interface incorporated 8-bit, 8-stage fifo (auto transfer for 1 to 8 bytes), 1 channel incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channnel incorporated two-wire 8-bit and 8-stage fifo (auto transfer for 1 to 8 bytes), 1 channel ?timer 8-bit timer/counter, 2 channels 19-bit time-base timer 32khz timer/counter ?high precision timing pattern generation ppg: maximum of 19 pins 32 stages programmable circuit rtg: 5 pins, 1 channel 7-bit, 10-satge fifo (recctl control/atc control), 1channel ?pwm/da gate output pwm: 12 bits, 2 channels (repetitive frequency 62.5khz at 16mhz) da gate pulse output: 13 bits, 2 channels ?analog signal input circuit pbctl amplifier circuit reel fg comparator ?ctl write/rewrite circuit recording current control circuit ?servo input control capstan fg, drum fg/pg, ctl, reel fg input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14 bits, 1 channel ?viss/vass circuit pulse duty auto detection circuit ?remote control receiving circuit 8-bit pulse measurement counter, 6-stage fifo ?tri-state output ppg output 2 pins ?high speed head switching circuit interruption 22 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp piggy/evaluation chip cxp88400 100-pin ceramic pqfp ?1 e98772a15-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic) structure silicon gate cmos ic
?2 CXP88452/88460 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0, 1, 6, 7 pe2 to pe5 pf0 to pf3 pf4 to pf7 pg0 to pg3 pi0 to pi7 rst extal clock generator/ system control ram 2048 bytes spc700 cpu core rom 52k/60k bytes interrupt controller 2 fifo frc capture unit avss av ref av dd a/d converter serial interface unit (ch2) fifo scl0 an0 to an11 int2 int0 12 8 port a 8 port b 8 port c port d 6 2 port e 4 4 port f 4 port g 4 port h 8 port i ph4 to ph7 a vss v dd mp xtal tx tex a int1/nmi prescaler/ time-base timer 32khz timer/counter 8 8-bit timer/counter 0 v sync separator 8-bit timer1 so1 rmc ctlfampi sync ec sck1 si1 to/ddo nmi 2 2 2 5 2 5 serial interface unit (ch0) ram serial interface unit (ch1) fifo daa1 daa0 14-bit pwm generator 12-bit pwm generator ch0 servo input control 12-bit pwm generator ch1 viss/vass remocon input fifo ctl r/w control pwm1 pwm0 pwm dpg dfg cfg exi1 exi0 headl ctlhead adj capstain drum pbctl amp reel comparator scl1 sda0 sda1 cs0 si0 so0 sck0 rfg0 rfg1 4 2 19 5 programable pattern generator ram realtime pulse generator ch0 ch1 fifo ph0 to ph3 ppo0 to ppo18 rto3 to rto7 4 block diagram
3 CXP88452/88460 pin assignment (top view) pe5/exi1 ph7 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 pe6/pwm0/daa0 pe7/pwm1/daa1 rfg0 rfg1 anout ampv dd ctlfampo ctlsampi ctlagnd ctlfampi ( ) ctlfampi (+) headl ( ) headl (+) ctlhead (+) ctlhead ( ) ampv ss v dd an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 ph6 ph5 ph4 ph3/sda1 ph2/sda0 ph1/scl1 ph0/scl0 mp rst v ss xtal extal pg3/ec/int2 pg2/dpg pg1/dfg pg0/cfg pf7/an11 pf6/an10 pf5/an9 pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pi7 pi6 pi5 pi4 pi3 pi2 pi1 pi0/int0 pd7/si0 pd6/so0 pd5/sck0 pd4/cs0 pd3/srvo/to/ddo/adj pd2/pwm pd1/rmc pd0/int1/nmi pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd v ss tx tex pe0/sck1 pe1/so1 pe2/si1 pe3/sync pe4/exi0 note) 1. nc (pin 90) is always connected to v dd . 2. v dd (pins 63 and 89) are both connected to v dd 3. vss (pins 41 and 88) are both connected to gnd. 4. mp (pin 39) is always connected to gnd.
4 CXP88452/88460 pin description (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. data is gated with ppo or rto contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port e) 8-bit port. bits 2, 3, 4 and 5 are for inputs; bits 0, 1, 6 and 7 are for outputs. (8 pins) programmable pattern generator (ppg) output. functions as high precision real- time pulse output port. (19 pins) pb0 and pb2 can be tri-state controlled with ppg. real-time pulse generator (rtg) output. functions as high precision real-time pulse output port. pc3 can be tri-state controlled with rtg. (5 pins) input pin to request external interruption and non-maskable interruption. remote control receiving circuit input pin. 14-bit pwm output pin. timer/counter, ctl duty detector, 32khz oscillation adjustment and servo amplifier output pin. serial chip select (ch0) input pin. serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial clock (ch1) i/o pin. serial data (ch1) output pin. serial data (ch1) input pin. composite sync signal input pin. external input pin for frc capture unit. (2 pins) symbol i/o description pa0/ppo0 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0/int1/ nmi pd1/rmc pd2/pwm pd3/to ddo/adj srvo pd4/cs0 pd5/sck0 pd6/so0 pd7/si0 pe0/sck1 pe1/so1 pe2/si1 pe3/sync pe4/exi0 pe5/exi1 pe6/pwm0/ daa0 pe7/pwm1/ daa1 pwm output pin. (2 pins) da gate pulse output pin. (2 pins) output/ real-time output output/ real-time output i/o/ real-time output i/o/ real-time output i/o/input/input i/o/input i/o/output i/o/output/output/ output/output i/o/input i/o/i/o i/o/output i/o/input output/i/o output/output input/input input/input input/input input/input output/output output/output head switching output.
5 CXP88452/88460 an0 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 pg0/cfg pg1/dfg pg2/dpg pg3/ec/ int2 ph0/scl0 ph1/scl1 ph2/sda0 ph3/sda1 ph4 to ph7 pi0/int0 pi1 to pi7 rfg0, rfg1 anout ctlfampo ctlsampi ctlagnd ctlfampi ( ) ctlfampi (+) headl ( ) headl (+) ctlhead ( ) ctlhead (+) ampv ss ampv dd input input/input output/input input/input input/input/input i/o/i/o output i/o/input i/o input output output input output input output i/o description i/o description (port f) lower 4 bits are for inputs; upper 4 bits are for outputs. lower 4 bits also serve as standby release input pins. (8 pins) (port h) 8-bit i/o port. upper four bits are for outputs. i/o can be set in a unit of single bits for lower four bits. lower four bits are n-ch open drain outputs and which can drive 12ma sink current. upper four bits are for outputs; n-ch open drain output of medium drive voltage (12v) and large current (12ma). (8 pins) input ports. (2 pins) output port. (1 pin) output port. (1 pin) input port. (1 pin) output port. (1 pin) input ports. (2 pins) output ports. (2 pins) i/o ports. (2 pins) analog signal input circuit gnd pin. analog signal input circuit power supply pin. input pin to request external interruption. active when falling edge. (port i) 8-bit i/o port. i/o can be set in a unit of single bits. function as standby release input can be set in a unit of single bits. (8 pins) analog input pin to a/d converter. (12 pins) (port g) 4-bit input port. (4 pins) capstan fg input pin. drum fg input pin. drum pg input pin. external event input pin for timer/counter. serial clock (ch2) i/o pin. serial data (ch2) i/o pin. input pin to request external interruption. active when falling edge. reel fg input pin. internal waveform output pin analog circuit. pbctl signal 1st amplifier output. pbctl signal 2nd amplifier input. smoothing capacitor connecting pin. input pbctl signal with capacitor coupled. during playback, connect to ctlhead ( ) and ctlhead (+) with internal signal. during playback, input pin of pbctl signal; during recording, output pin of pbctl signal.
6 CXP88452/88460 extal xtal tex tx rst nc mp av dd av ref av ss v dd v ss input output input output input input input symbol i/o description connecting pin of crystal oscillator for system clock. when supplying the external clock, input it to extal pin and input the opposite phase clock to xtal pin. connecting pin of crystal oscillator for 32khz timer clock. when used as event counter, input to tex pin and leave tx pin open. (in this time, feedback resistor is not removed.) system reset pin; active at low level. nc pin. connect this pin to v dd for normal operation. test mode input pin. always connect to gnd. positive power supply pin of a/d converter. reference voltage input pin of a/d converter. gnd pin of a/d converter. positive power supply pin. gnd pin. connect both vss pins to gnd.
7 CXP88452/88460 input/output circuit formats for pins aaaaa aaaaa aa aa ppo data internal data bus output becomes active from high impedance by data writing to port data register. ports a and b data rd (port a or port b) port a 2 pins 2 pins hi-z hi-z hi-z after a reset pb0/ppo8 pb2/ppo10 pb1/ppo9 pb3/ppo11 pa0/ppo0 to pa7/ppo7 pb4/ppo12 to pb7/ppo15 port b 12 pins port b pin circuit format output becomes active from high impedance by data writing to port data register. ppo9, ppo11 data aa aa aaaa aaaa pb1, pb3 data ppo9, ppo11 data aaaa a aa a aaaa ppg control/status register bit 0 tri-state control selection rd (port b) internal data bus output becomes active from high impedance by data writing to port data register. internal data bus rd (port b) aaaa aaaa pb0, pb2 data ppo8, ppo10 data aa aa "0" after a reset
8 CXP88452/88460 ppo, rto data aaaa aaaa a a port c direction aaaa aaaa port c data ip a a input protection circuit internal data bus rd (port c) rd (port c direction) internal data bus "0" after a reset 6 pins after a reset pc0/ppo16 to pc2/ppo18 pc5/rto5 to pc7/rto7 hi-z pin circuit format rto3 data internal data bus rd (port c) aaa aaa pc3 direction aaa aaa pc3 data aa aa a a ip "0" after a reset rto4 data aaaa a aa a aaaa rtg interruption control register bit 7 tri-state control selection rd (port c) aaa aaa pc4 direction aaa aaa pc4 data aa aa a ip rto4 data "0" after a reset internal data bus internal data bus rd (port c direction) internal data bus rd (port c direction) "0" after a reset hi-z pc3/rto3 hi-z pc4/rto4 1 pin 1 pin port c port c
9 CXP88452/88460 after a reset port d port d pin circuit format aa aa aaaa aaaa port d data a a ip internal data bus rd (port d) aaaa aaaa port d direction pd1: remote control circuit pd0: interruption circuit pd4, pd7: serial ch0 schmitt input internal data bus rd (port d direction) "0" after a reset aa aa aaa a a a a a a aaa pd2: 14-bit pwm timer/counter, ctl duty detection circuit, 32khz timer, amplifier circuit mpx aaaa port d data aa aa ip internal data bus rd (port d) aaaa port d direction aaa aaa port d function select rd (port d direction) internal data bus pd3: "0" after a reset "0" after a reset hi-z pd0/int1/nmi pd1/rmc pd4/cs0 pd7/si0 hi-z pd2/pwm pd3/srvo/ to/ddo/ adj 4 pins 2 pins a a aa aa aa aa mpx aaaa aaaa port d data aa aa ip internal data bus rd (port d) aaaa aaaa port d direction aaaa aaaa port d function select aaa a a a a a a aaa mpx sio ch0 sio ch0 note) pd5 is schmitt input pd6 is inverter input "0" after a reset "0" after a reset 2 pins pd5/sck0 pd6/so0 hi-z port d
10 CXP88452/88460 internal data bus rd (port e) aaaa aaaa aa aa aa aa aa aa da gate output or pwm output hi-z control mpx aaaa aaaa port e data port/da/pwm select "1" after a reset 2 pins pe6/pwm0/ daa0 pe7/pwm1/ daa1 high level port e internal data bus rd (port e) aaaa aaaa aa aa aa aa aa aa sio ch1 hi-z control mpx aaaa aaaa port e data port e function select "1" after a reset internal data bus rd (port e) aaaa aaaa aa aa aa aa aa aa sio ch1 hi-z control mpx aaaa aaaa port e data port/sck output select a a ip sio ch1 "1" after a reset port e hi-z hi-z hi-z after a reset pe0/sck1 port e port e 1 pin 1 pin 4 pins pe1/so1 pe2/si1 pe3/sync pe4/exi0 pe5/exi1 pin circuit format aa aa ip rd (port e) internal data bus schmitt input pe2: sio ch1 pe3 pe4 : servo input pe5 note) for pe3/sync, cmos schmitt input or ttl schmitt input can be selected with the mask option.
11 CXP88452/88460 4 pins hi-z hi-z hi-z after a reset pf4/an8 to pf7/an11 3 pins an0 to an3 4 pins pf0/an4 to pf3/an7 pin circuit format aa aa aaaa aaaa port f data aa aa ip internal data bus rd (port f) aaaa port/ad select a/d converter input multiplexer "1" after a reset aa aa aa aa ip input multiplexer a/d converter port f rd (port f) internal data bus aa aa aa aa ip input multiplexer a/d converter port f hi-z pg0/cfg pg1/dfg pg2/dpg aa aa ip rd (port g) internal data bus schmitt input servo input schmitt width selection power on/off control port g 3 pins hi-z pg3/ec/int2 aa aa ip rd (port g) internal data bus schmitt input port g 1 pin
12 CXP88452/88460 pin after a reset circuit format 4 pins hi-z ph4 to ph7 internal data bus rd (port h) aa aa aaaa aaaa port h data ? 12v drive voltage, large current 12ma ? port h 4 pins hi-z ph0/scl0 ph1/scl1 ph2/sda0 ph3/sda1 scl, sda a a aaaa aaaa port h direction aaaa aaaa port h data ip aa aa internal data bus rd (port h) rd (port h direction) internal data bus i 2 c output enable schmitt input other serial interface (ch2) pin) scl, sda (serial interface (ch2) circuit) "0" after a reset port h 1 pin hi-z pi0/int0 aaa aaa pi0 direction aaa aaa pi0 data aa aa aaa aaa pull-up resistor aa aa ip internal data bus rd (port i) rd (port i direction) rd (pull-up resistor) internal data bus internal data bus standby release interruption circuit edge detection aa aa ? pull-up transistors approx. 100k ? ? "0" after a reset "0" after a reset port i
13 CXP88452/88460 pin after a reset circuit format 7 pins hi-z pi1 to pi7 aaa aaa port i direction aaa aaa port i data aa aa aaa aaa pull-up resistor aa aa ip ? internal data bus rd (port i) rd (port i direction) rd (pull-up resistor) internal data bus internal data bus standby release edge detection aa aa ? pull-up transistors approx. 100k ? "0" after a reset "0" after a reset port i aaaaa aaaaa input pin charge control a a aa aa ip aa aa ip a a a a ctlfampi ( ) ctlfampi (+) a a aa aa ctlfampo a ctlagnd 3 pins 1/2ampv dd ctlfampi (+) ctlfampi ( ) ctlfampo ctlsampi 1 pin 1/2ampv dd aaaa aaaa input pin charge control aa aa ip aa aa lpf circuit aa aa ctlagnd
14 CXP88452/88460 a aa ip ampv ss rtg control permission rto3 ctlhead ( ) pin aa aa aa aa ip headl (+) pin aa aa recording current control circuit ampv ss write current select rtg control permission rto6 rto7 rto3 ampv dd 1 pin 1 pin hi-z hi-z hi-z after a reset ctlhead (+) headl ( ) ctlhead ( ) 1 pin 1 pin hi-z headl (+) pin circuit format a aa ip ampv ss rtg control permission rto3 ctlhead (+) pin aa aa aa aa ip headl ( ) pin aa aa recording current control circuit ampv ss write current select rtg control permission rto7 rto6 rto3 ampv dd 1 pin 1/2ampv dd ctlagnd aa aa ampv dd aa aa ip ampv ss ctl amp
15 CXP88452/88460 2 pins oscillation pin after a reset circuit format extal xtal aa aa aa aa ip aa aa extal xtal shows the circuit composition during oscillation. feedback resistor is removed and xtal outputs high level during stop. 2 pins oscillation tex tx aa aa aa aa ip aa aa tex tx shows the circuit composition during oscillation. feedback resistor is removed during 32khz oscillation circuit stop by software. at that time, tex pin outputs low level and tx pin outputs high level. 32khz timer/counter 1 pin low level (during a reset) rst aa aa aa ip schmitt input pull-up resistor op mask option 2 pins hi-z rfg0 rfg1 aa aa a ip comparator servo output
16 CXP88452/88460 ? 1 av dd should not exceed v dd + 0.3v. ? 2 ampv dd should not exceed v dd + 0.3v. ? 3 v in and v out should not exceed v dd + 0.3v. ? 4 the large current output port is port h (ph7 to ph4). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss ampv dd ampv ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 avss to +7.0 ? 1 0.3 to +0.3 ampv ss to +7.0 ? 2 0.3 to +0.3 0.3 to +7.0 ? 3 0.3 to +7.0 ? 3 0.3 to +15.0 5 50 15 20 130 20 to +75 55 to +150 600 v v v v v v v v ma ma ma ma ma c c mw port h (ph7 to ph4) pin total of output pins other than large current output ports (value per pin) large current output port ? 4 (value per pin) total of output pins qfp package type item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
17 CXP88452/88460 analog supply voltage high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 4.5 4.5 0.7v dd 0.8v dd 2.2 v dd 0.4 0 0 0 0.3 20 av dd ampv dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing clock guaranteed operation range for 1/16 frequency dividing clock or during sleep mode guaranteed operation range by tex clock guaranteed data hold operation range during stop ? 1 ? 2 ? 3 cmos schmitt input ? 4 ttl schmitt input ? 5 extal pin ? 6 tex pin ? 7 ? 3 cmos schmitt input ? 4 ttl schmitt input ? 5 extal pin ? 6 tex pin ? 7 v dd ? 1 av dd and v dd should be set to the same voltage. ? 2 ampv dd and v dd should be set to the same voltage. ? 3 normal input port (each pin of pc, pd2, pd3, pd6, pf0 to pf3, pi1 to pi7 and ph0 to ph3), mp pin ? 4 each pin of rst, pd0/int1/nmi, pd1/rmc, pd4/cs0, pd5/sck0, pd7/si0, pe0/sck1, pe2/si1, pe3/sync, pe4/exi0, pe5/exi1, pi0/int0, pg3/ec/int2 (for pe3/sync, when cmos schmitt input is selected with mask option.) ? 5 pe3/sync (when ttl schmitt input is selected with mask option.) ? 6 specifies only during external clock input. ? 7 specifies only during external event input. recommended operating conditions (vss = 0v reference)
18 CXP88452/88460 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 0.5 0.1 0.1 1.5 v v v v v a a a a a a a ph extal tex rst ? 1 item symbol pins conditions min. v dd, v ss i dd1 i iz i loh i dds1 i dd2 i dds2 i dds3 v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 40 10 10 400 10 50 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = 20 to +75 c, vss = 0v reference) v dd = 5.5v ? 3 sleep mode v dd = 5.5v v dd = 5v 0.5v supply current ? 2 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12v v dd = 5.5v, v oh = 5.5v 16mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current (n-ch tr off state) pa to pf, pg3, pi, mp, an0 to an3, rst ? 1 ph4 to ph7 ph0 to ph3 37 2.1 58 9 50 8 100 35 10 ma ma a a a v dd = 3.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf) pa to pd, pe0 to pe1, pe6 to pe7, pf4 to pf7, ph (v ol only) pi 10 a
19 CXP88452/88460 ? 1 rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistor is selected. ? 2 when entire output pins are left open. ? 3 when setting upper 2 bits (cpu clock selection) of clock control register (clc: 00feh) to "00" and operating in high speed mode (1/2 frequency dividing clock). item symbol pins conditions min. clock 1mhz 0v other than the measured pins c in typ. max. unit input capacity 10 20 pf pc, pd, pe0, pe2 to pe5, pf, pg, pi, ctlhead (+), ctlhead ( ), ctlfampi (+), ctlfampi ( ), ctlsampi, rfg, xtal, tex
20 CXP88452/88460 tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing ? 1 t sys indicates three values according to the contents of the clock control register (clc; 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") extal xtal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaa aaaa external clock extal xtal 74hc04 aaaa aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 aaaa aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 typ. 32.768 min. 1 28 t sys + 200 ? 1 10 max. 16 200 20 20 (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing fig. 2. clock applied condition
21 CXP88452/88460 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (clc; 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck0 output mode and so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 sck0 delay time cs0 sck0 floating delay time cs0 so0 delay time cs0 so0 floating delay time cs0 high level width sck0 cycle time sck0 high and low level widths si0 input set-up time (against sck0 ) si0 input hold time (against sck0 ) sck0 so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pins min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 100 t sys + 100 200 2 t sys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 t sys + 100 100 max. unit conditions
22 CXP88452/88460 fig. 4. serial transfer timing (ch0) cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
23 CXP88452/88460 serial transfer (ch1) (sio mode) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pins min. max. unit conditions sck1 cycle time sck1 high and low level widths si1 input setup time (for sck1 ) si1 input hold time (for sck1 ) sck1 so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 2 t sys + 200 16000/fc t sys +100 8000/fc 50 100 200 t sys + 200 100 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc: 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing (sio mode) sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
24 CXP88452/88460 so1 cycle time si1 data setup time si1 data hold time t lcy t lsu t lhd so1 si1 si1 si1 ? 1 2 2 104 s s s item symbol pins conditions min. typ. max. unit serial transfer (ch1) (special mode) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) ? 1 t lcy is specified only when serial mode register (ch1) (siom1: 05f2h) lower 2 bits (so1 clock selection) are set at 104s. note) the load of so1 pin is 50pf + 1ttl. fig. 6. serial transfer ch1 timing (special mode) so1 si1 t lcy start bit output data bit t lcy 0.5v dd 0.8v dd 0.2v dd t lcy/2 t lsu t lhd input data bit
25 CXP88452/88460 serial transfer (ch2) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repeated transfers data hold time data set-up time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 2.6 1.0 1.0 1.0 1.0 0 ? 1 100 1.6 400 300 300 khz s s s s s s ns ns ns s symbol pins conditions min. max. unit ? 1 the scl fall time (300ns max.) is not included in the data hold time. fig. 7. serial transfer timing (ch2) p st t su; sto t su; sta t hd; sta t su; dat t high t hd; dat t f t r t low t hd; sta s p t buf sda scl fig. 8. device recommended circuit device device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor (r p ) must be connected to sda0 (or sda1) and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 ? or less) can be used to reduce the spike noise caused by crt flashover.
26 CXP88452/88460 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v operating mode sleep mode stop mode 32khz operating mode linearity error absolute error resolution av ref current av ref i ref s s v v av dd av ref 1.0 ma 10 a 0.6 160/f adc ? 1 12/f adc ? 1 av dd 0.5 0 item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (ta = 20 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) 8 1 2 lsb lsb analog input linearity error 00h 01h feh ffh digital conversion value v zt v ft fig. 9. definitions of a/d converter terms an0 to an7 av ref ? 1 f adc indicates the below values due to the peripheral clock control register (pcc: 05f8h) bit 3 and clock control register (clc: 00feh) upper 2 bits. adcck pck1, pck0 00 ( = f ex /2) 01 ( = f ex /4) 11 ( = f ex /16) f adc = fc/2 f adc = fc/4 f adc = fc/16 f adc = fc f adc = fc/2 f adc = fc/8 0 ( /2 selection) 1 ( selection)
27 CXP88452/88460 (5) others (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cfg input high and low level widths dfg input high and low level widths dpg minimum pulse width dpg minimum removal time exi input high and low level widths t cfh t cfl t dfh t dfl t dpw t rem t eih t eil cfg dfg dpg dpg exi0 exi1 ns ns ns ns ns symbol pins min. 24 t frc + 200 16 t frc + 200 8 t frc + 200 16 t frc + 200 8 t frc + 200 + t sys max. unit t sys = 2000/fc conditions note 1) t frc = 1000/fc [ns] note 2) t sys indicates three values according to the contents of the clock control register (clc: 00feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") external interruption high and low level widths reset input low level width int0 int1 int2 nmi pi0 to pi7 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 nmi pi0 to pi7 (during standby release input) (falling edge) fig. 10. interruption input timing t rsl 0.2v dd rst fig. 11. reset input timing
28 CXP88452/88460 0.8v dd cfg t cfh t cfl 0.2v dd 0.8v dd dfg t dfh t dfl 0.2v dd 0.8v dd t dpw t rem dpg 0.8v dd exi0 exi1 t eih t eil 0.2v dd t rem fig. 12. other timings
29 CXP88452/88460 voltage gain ? 1 output offset voltage lpf cut-off frequency item symbol pins conditions min. typ. max. unit db mv khz (3) ctl 2nd amplifier characteristics (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) gain = 5db gain = 8db gain = 11db gain = 14db gain = 17db gain = 20db ctlsampi = open, gain = 5db 12khz, f dc 3db 20khz, f dc 3db a vctl2 v osctl2 f cctl ctlsampi ctlsampi ctlsampi 3.5 6.2 9.0 12.0 15.0 18.0 30 8 12 5.5 8.2 11.0 14.0 17.0 20.0 0 12 20 7.5 10.2 13.0 16.0 19.0 22.0 +30 24 42 voltage gain ? 1 output offset voltage item symbol pins conditions min. typ. max. unit db mv (2) ctl 1st amplifier characteristics (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) ctlfampi ( ) = 0v, gain = 16db ctlfampi ( ) = 0v, gain = 34db ctlfampi ( ) = 0v, gain = 49db ctlfampi ( ) = 0v, gain = 55db ctlfampi ( ), ctlfampi (+) = open, gain = 16db a vctl1 v osctl1 ctlfampi ( ) ctlfampi (+) ctlfampi ( ) ctlfampi (+) 13.5 31.8 46.5 52.5 25 15.5 33.8 48.5 54.5 0 17.5 35.8 50.5 56.5 +25 ? 1 the result after monitoring ctlfampo pin when the electrolytic capacitor (10f) is connected to ctlfamp ( ) and ctlfamp (+). reference level output voltage v or ctlagnd item symbol pins conditions min. typ. max. unit v (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) 2.75 2.20 2.45 analog circuit characteristics (1) amplifier circuit reference voltage characteristics
30 CXP88452/88460 ? 1 the result after monitoring anout pin when the electrolytic capacitor (10f) is connected to ctlsampi. ? 2 the reference value of the comparator level is ctlagnd. voltage gain ? 3 input sensitivity item symbol pins conditions min. typ. max. unit db vp-p (4) ctl amplifier characteristics (ctl1stamp + ctl2ndamp) (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) ctlhead ( ) = 0v, gain = (16db + 5db) ctlhead ( ) = 0v, gain = (55db + 20db) ctlhead ( ) = 0v, gain = (55db + 20db) comparator = 150mv 0-p a vctl v sctl ctlhead ( ) ctlhead (+) ctlhead ( ) ctlhead (+) 17.0 70.5 60 20.5 74.5 70 23.5 77.0 140 ? 3 the result when waveform is input from ctlhead (+) pin and anout pin is monitored after performing coupling electrolytic capacitor (10f) of ctlhead ( ) and ctlhead (+), and coupling electrolytic capacitor (10f) of headl ( ) and headl (+), ctlfampi ( ) and ctlfampi (+) , and ctlfampo and ctlsampi. gain is maximum 1.5db lowered when waveform is input from ctlhead (+) pin. comparator level ? 2 item symbol pins conditions min. typ. max. unit mv comparator level = +100mv 0-p comparator level = +150mv 0-p comparator level = +200mv 0-p comparator level = +250mv 0-p comparator level = +300mv 0-p comparator level = +400mv 0-p comparator level = +500mv 0-p comparator level = +600mv 0-p comparator level = +1000mv 0-p comparator level = 100mv 0-p comparator level = 150mv 0-p comparator level = 200mv 0-p comparator level = 250mv 0-p comparator level = 300mv 0-p comparator level = 400mv 0-p comparator level = 500mv 0-p comparator level = 600mv 0-p comparator level = 1000mv 0-p v cctl ctlsampi 80 110 160 210 250 340 420 530 850 90 110 150 200 240 340 430 540 870 110 150 200 250 290 380 470 570 920 120 130 190 240 280 380 480 580 970 140 190 240 290 330 420 520 610 990 150 190 230 280 320 420 530 620 1070
31 CXP88452/88460 atc peak hold circuit initialize voltage value ? 2 atc comparator level offset voltage ? 3 item symbol pins conditions min. typ. max. unit mv mv (6) auto threshold control circuit (atc) characteristics (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) voltage = 150mv 0-p voltage = 400mv 0-p gain = 1/6 (16.7%) gain = 1/5 (20%) gain = 1/4 (25%) gain = 1/3 (33.3%) gain = 2/5 (40%) gain = 1/2 (50%) gain = 3/5 (60%) v atcinit v atcoff 110 350 150 400 70 90 90 70 90 70 90 190 450 160 210 210 160 210 160 210 ? 2 reference is ctlagnd. ? 3 reference is ctlagnd. when comparator level is generated using atc, actual comparator level is as follows by the offset voltage inside of atc. vin gain + |offset voltage| example: gain = 1/2 vin 1/2 + 160 rtg schmitt width cfg/dfg/dpg item symbol pins conditions min. typ. max. unit mv mv (7) schmitt characteristics (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) schmitt width 1vp-p schmitt width 410mvp-p schmitt width 1vp-p s rfg rfg0, rfg1 s cfg s dfg s dpg cfg, dfg, dpg 820 180 700 920 300 900 1020 420 1100 write current ? 1 item symbol pins conditions min. typ. max. unit ma (5) recctl write circuit characteristics (ampv dd = v dd = 5.0v, ampv ss = vss = 0v, ta = 20 to +75 c) write current 2.0map-p write current 3.0map-p write current 4.0map-p write current 5.0map-p write current 6.0map-p write current 7.0map-p write current 8.0map-p write current 9.0map-p write current 10.0map-p i orec ctlhead ( ) ctlhead (+) 0.8 1.4 2.0 2.4 3.0 3.5 4.5 5.0 5.5 1.8 2.8 3.8 4.8 6.0 6.8 7.8 8.8 7.7 3.6 5.0 7.0 8.5 10.0 11.5 13.0 15.0 17.0 ? 1 the current which flows when ctlhead ( ) and ctlhead (+) shorts.
32 CXP88452/88460 appendix aaaa a aa a aaaa extal xtal c 1 c 2 rd (i) aaaa a aa a aaaa tex tx c 1 c 2 rd (ii) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 16.00 12 12 10 5 16 (12) 16 (12) 10 16.00 5 16 (12) 16 (12) 0 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (i) 470k (ii) mask option table 12.00 12 12 32.768khz 18 30 ? 1 the input circuit format can be selected for pe3/sync pin. item content reset pin pull-up resistor input circuit format ? 1 non-existent cmos schmitt existent ttl schmitt fig. 13. recommended oscillation circuit
33 CXP88452/88460 023456 0.01 (10a) 0.1 (100a) 1 10 100 0 5 10 15 i dd vs. v dd (fc = 16mhz, ta = 25 c, w 0 9) i dd supply current [ma] v dd supply voltage [v] 32khz sleep mode i dd vs. fc (v dd = 5.0v, ta = 25 c, w 0 9) fc system clock [mhz] sleep mode 1/16 dividing mode 1/2 dividing mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode 1/4 dividing mode 32khz mode i dd supply current [ma] 40 20 10 0 30 characteristics curve
34 CXP88452/88460 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2
35 CXP88452/88460 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony corporation

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